A data processor functions in response to machine code instructions. A machine code instruction set may have all instructions of the same length, or may have variable-length instructions. How the machine code instructions are organized depends largely on the specification of the machine code. Common to most organisations is the division of the instruction into one field, the opcode (operation code) which specifies the exact operation (for example “add”) and other fields, which may give the type of the operands, their location, or their value directly (operands contained in an instruction are called immediate). The specification and format of the instructions are laid out in the instruction set architecture of the processor in question (which may be a general central processor unit (‘CPU’) or a more specialized processing unit). The location of an operand may be a register or a memory. The types of operations may include arithmetics, logical operations and data instructions including display or print characters for example, as well as special instructions (such as CPUID and others) and program control.
U.S. Pat. No. 4,649,477 describes certain issues arising with instruction execution in a typical data processor, such as a microcontroller or a microprocessor. The instructions are partitioned into functional routines. These routines perform either a portion of the instruction or the entire instruction, depending on the instruction's complexity. An example is the fetch effective address routine which calculates an effective address and then fetches the sized operand from that address. To perform this operation, it is necessary to provide size information during the address calculation operation. The size is also needed by the bus controller to determine the size of the operand to be fetched from memory. These routines require that the instruction be decoded to reflect the size of the operand to be fetched. Similarly, the instruction operation routine which performs the operation on the operands for the instruction may require their size.
In a machine which performs operations on various sized operands that is controlled by a control structure, it is possible to provide different control sequences for each sized operation. This technique is inefficient, however, for while it is necessary to provide separate control for those operations larger than the size of the available resources, it would be preferable that all sizes less than or equal to those resources should share control sequences and allow secondary decoding of the instruction and provide the determination as to which size should occur.
If there is sharing of code sequences for multiple operations as well as multiple operand sizes, the constraints become more stringent. As an example, there are functional routines provided to evaluate an effective address and to fetch the sized operand. U.S. Pat. No. 4,649,477 refers to data processors having a 16 bit data bus in which there are two different routines, one to fetch a long word operand and the other to fetch a byte or a word operand depending upon the size of the operation. These routines can be called in the execution of any instruction.
U.S. Pat. No. 4,649,477 refers to data processors which perform operations on operands which have their size or length specified as part of the instruction, the operand and register size being controlled implicitly. The size of the operation normally reflects the size of the operand to be operated on for an instruction. There are three operand sizes handled in the examples of processors referred to, namely 8-, 16- and 32-bit operands to perform byte, word and long word operations, respectively. The control used to perform sized operations is derived from the instruction and affects the execution unit, condition codes in the condition code register, the data bus and the bus controller. Other operand sizes are also possible, notably 64-bit, for example.
U.S. Pat. No. 4,649,477 proposes a data processor which has an instruction register for storing an instruction which selects the operation to be performed on the operand and the size of the operand, and a size controller for selectively enabling either the instruction register or another functional block, or a size selector to select the size of the operand so as to allow both implicit residual size control, where the size is calculated by one of several control units, and explicit size control, where the size is selected or forced by the size selector.
U.S. Pat. No. 4,649,477 aims in this way to achieve a simplification in the internal state machine based on selecting the operand sizes by an internal size bus where different sized operands are needed. However, when employing explicit control it applies the same operand size to each register and does not enable dynamic switching of the register sizes, that is to say making the register size part of a task state.